Several material systems have emerged as key facilitators to extend Moore's law well into the next decade. These key facilitators include (1) silicon-on-insulator (SOI), (2) silicon-germanium (SiGe), and (3) strained silicon. With reference to SOI and related technologies, there are numerous advantages associated with an insulating substrate. These advantages include reduced parasitic capacitances, improved electrical isolation, and reduced short-channel-effects. Advantages of SOI can be combined with energy bandgap and carrier mobility improvements offered by Si1-xGex and strained silicon devices.
SOI substrates generally include a thin layer of silicon on top of an insulator. Integrated circuit components are formed in and on the thin layer of silicon. The insulator can be comprised of insulators such as silicon dioxide (SiO2), sapphire, or various other insulative materials.
Currently, several techniques are available to fabricate SOI substrates. One technique for fabricating SOI substrates is separation by implantation of oxygen (SIMOX). In a SIMOX process, oxygen is implanted below a surface of a silicon wafer. A subsequent anneal step produces a buried silicon dioxide layer with a silicon overlayer. However, the time required for an implantation in a SIMOX process can be extensive and, consequently, cost prohibitive. Moreover, an SOI substrate formed by SIMOX may be exposed to high surface damage and contamination.
Another technique is bond-and-etch-back SOI (BESOI) where an oxidized wafer is first diffusion-bonded to a non-oxidized water. With reference to FIG. 1A, a silicon device wafer 100 and a silicon handle wafer 150 comprise major components for forming a BESOI wafer. The silicon device wafer 100 includes a first silicon layer 101, which will serve as a device layer, an etch-stop layer 103, and a second silicon layer 105. The etch-stop layer 103 is frequently comprised of carbon. The silicon handle wafer 150 includes a lower silicon dioxide layer 107A, a silicon substrate layer 109, and an upper silicon dioxide layer 107B. The lower 107A and upper 107B silicon dioxide layers are frequently thermally grown oxides formed concurrently.
In FIG. 1B, the silicon device water 100 and the silicon handle water 150 are brought into physical contact and bonded, one to the other. The initial bonding process is followed by a thermal anneal, thus strengthening the bond. The silicon device wafer 100 in the bonded pair is thinned. Initially, most of the second silicon layer 105 is removed by mechanical grinding and polishing until only a few tens of micrometers (i.e. “microns” or μm) remain. A high-selectivity wet or dry chemical etch removes remaining portions of the second silicon layer 105, stopping on the etch-stop layer 103. (Selectivity is discussed in detail, below.) An end-result of the second silicon layer 105 etch process is depicted in FIG. 1C.
During the etching process the silicon handle wafer 150 is protected by a coated mask layer (not shown). In FIG. 1D, the etch-stop layer 103 has been removed using another high-selectivity etchant. As a result of these processes, the first silicon layer 101, serving as a device layer, is transferred to the silicon handle wafer 150. A backside of the silicon substrate layer 109 is ground, polished, and etched to achieve a desired overall thickness.
To ensure BESOI substrates are thin enough for subsequent fabrication steps as well as meeting contemporary demands for ever-decreasing physical size and weight constraints, BESOI requires the presence of the etch-stop layer 103 during the layer transfer process. Currently, two main layer transfer technologies exist: 1) splitting of a hydrogen-implanted layer from a device layer (a hydrogen implantation and separation process), and 2) selective chemical etching. Both technologies have demonstrated they meet requirements of advanced semiconductor processing.
In the hydrogen implantation and separation process, hydrogen (H2) is implanted into silicon having a thermally grown silicon dioxide layer. The implanted H2 produces embrittlement of the silicon substrate underlying the silicon dioxide layer. The H2 implanted wafer may be bonded with a second silicon wafer having a silicon dioxide overlayer. The bonded wafer may be cut across the wafer at a peak location of the hydrogen implant by appropriate annealing.
The BESOI process described is relatively free from ion implant damage inherent in the SIMOX process. However, the BESOI process requires a time consuming sequence of grinding, polishing, and chemical etching.
Contemporary Etch-Stops
As described above, the BESOI process is a manufacturing-oriented technique to build silicon on insulator substrates and is partially dependent upon chemical retching.
Etch-stop performance is described by a mean etch selectivity, S, which defines an etch rate ratio of silicon to the etch-stop layer
  S  =            R      si              R      es      where RSi is an etch rate of silicon and Res is an etch rate of the etch-stop. Therefore, a selectivity value where S=1 relates to a case of no etch selectivity.
One method to evaluate etch-stop efficiency is to measure a maximum etch step height across etch-stop and non-etch-stop boundaries. In FIG. 2A, an etch-stop 203A is formed by ion implantation into a portion of a silicon substrate 201A. The etch-stop 203A has a thickness d1 at time t=0 (i.e., prior to application of any etchant). At time t=t1 (FIG. 2B), a partially etched silicon substrate 201B is etched to a depth h1. The etch-stop 203A is now a, partially etched etch-stop 203B. The partially etched etch-stop 203B is etched to a thickness of d2. At time t=t2 (FIG. 2C), the partially etched etch-stop 203B (see FIGS. 2A and 2B) has been completely etched and a fully etched silicon substrate 201C achieves a maximum etch step height of h2. An etch rate of the etch-stop 203A (FIG. 2A) is partially dependent upon both a dopant material implanted as well as an implant profile of the dopant employed. From a practical point of view, the maximum etch step is a critical quantity since it determines an acceptable thickness variation of the device wafer after grinding and polishing prior to etch back, in the BESOI process.
For example, if a maximum etch step is 3 units, the allowable thickness non-uniformity of the device wafer after the usual mechanical thinning procedure should be less than 1.5 units. The mean etch selectivity, S, can be derived from the effective etch-stop layer thickness d1 and the maximum etch step h2 as
      S    =                                        d            1                    +                      h            2                          t                              d          1                t                                ⇓                                      S          =                      1            +                                          h                2                                            d                1                                                        where t is the etch time required to reach the maximum etch step height h2. In the prior example, t2 is the etch time required to reach the maximum etch step height h2.
In addition to problems created by reduced selectivity, other problems may arise with using carbon or boron as an etch-stop. A skilled artisan recognizes that carbon diffuses readily in a pure silicon and thus the etch-stop layer readily increases in thickness. Boron also diffuses readily in silicon and grows in thickness after subsequent anneal steps. Carbon and boron etch-stop layers of the prior art are frequently hundreds of nanometers in width (at full-width half-maximum (FWHM)). Therefore, what is needed is an extremely thin and robust etch-stop layer having a high etchant selectivity in comparison with silicon.